What’s New – Pep/9 Micro Simulator
This version is the result of a refactorization that consolidates the code from four different applications – Pep/9, Pep/9 CPU, Pep/9 Terminal, and Pep/9 Micro – into a single suite of software for ease of maintenance. This is the first release of the Pep/9 Micro application.
Pep/9 Micro extends the microinstruction format of Pep/9 CPU to allow conditional microcode branches. The microcode now implements the complete von Neumann cycle, including the decode logic necessary to execute every Pep/9 ISA instruction. It has the following features.
- The Micro IDE includes the assembler from
Pep9and the CPU simulator from
Pep9CPUso that complete assembly language programs can be executed at the microcode level spanning two levels of abstraction.
- It can run both memory aligned and nonaligned programs. Assembly language programs that do not use optimal
.ALIGNdirectives still execute correctly but slower.
- It provides performance statistics in the form of statement execution counts at the microcode level and the ISA level. Students can measure the performance differences between aligned and nonaligned programs.
- It retains the unit tests of the original Pep/9 IDE so that students can write microcode fragments with the extended microinstruction format.
- It retains the symbolic memory trace feature of the original IDE. Assembly language programs with valid trace tags produce visual global variable, stack frame, and heap renderings when executing in debug mode.
- It retains the operating system with the trap handlers from Computer Systems. Students can implement new trap instructions as in the original Pep/9 application.
- It supports common debugging features like step-into, step-out, and step-over so students can trace program execution at both the microcode and the ISA level.
The microcode implementation of Pep/9 required a few slight changes to the system. In Computer Systems, the input port is at an odd address and the output port is at an even address. Because the microcode system simulates the two-byte data bus, the input and output ports of the operating system are aligned to even addresses.
In Computer Systems, there are two unary no-operation traps,
NOP1, and five nonunary traps,
STRO. This application makes two modifications to these instructions.
First, this implementation makes
NOP0 a native no-operation instruction, not a trap instruction. Now it can legitimately be used to align assembly language program statements without the trap performance penalty.
Second, at the ISA3 level the execution model in Computer Systems distinguishes between two types of traps, unary and nonunary. It must decode the opcode and increment the program counter differently for the two types of instructions. In this implementation, all traps are unary at the ISA level, and it is the operating system’s job to increment the program counter the extra two bytes for the operand specifier of the nonunary trap instructions. These changes simplify the overall design at the ISA3 level and the implementation at the Mic2 level.
These changes are all invisible at the Asmb5 level. The compilation process from level HOL6 to Asmb5 is also unchanged. The only visible difference is in some machine language object code like the values of the
charOut symbols that identify the memory-mapped I/O ports, and the initial value of the stack pointer.